1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of strain-inducing mechanisms.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch contact layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 3 Giga Pascal (GPa) or higher of compressive stress and up to 2 GPa and higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
When forming two types of stressed layers, however, these strain-inducing mechanisms may suffer from a reduced efficiency when device dimensions are increasingly scaled down, for instance in the 45 nm technology and further advanced approaches, due to the limited conformal deposition capabilities of the deposition processes involved. That is, for a given maximum internal stress level that may be achieved in the dielectric materials, typically the amount of the stressed dielectric material that may be positioned close to the channel region of the transistors may be restricted by the deposition capabilities of the associated deposition techniques. Furthermore, upon further scaling the overall transistor dimensions, in particular in device regions including a large number of transistors that are closely packed, the overall performance of the transistor elements may increasingly be influenced by the contact elements connecting to the drain and source regions of the closely packed transistors. In this case, it has been observed that drive current capability and thus transistor performance may strongly depend on the characteristics and the configuration of a contact structure, as will be described with reference to FIGS. 1a and 1b in more detail.
FIG. 1a schematically illustrates a top view of a sophisticated semiconductor device 100 comprising a plurality of closely packed transistor elements of which an N-channel transistor 150A and a P-channel transistor 150B are illustrated for convenience. For example, the transistors 150A, 150B may represent any transistors in closely packed device regions, such as static RAM (random access memory) areas and the like. An active region 102A may be defined by an isolation structure 103, for instance in the form of a shallow trench isolation and may comprise drain and source regions (not shown) of the transistor 150A and possibly of other transistors that may be formed on the basis of the active region 102A. Similarly, the transistor 150B comprises an active region 102B defined by the isolation structure 103. Moreover, a gate electrode structure 151 may be formed above the active regions 102A and 102B, respectively, and may extend above the isolation structure 103. The gate electrode structures 151 may be of any appropriate configuration and may have critical dimensions in accordance with the overall design rules. Thus, the transistors 150A, 150B may have a transistor width direction, indicated as W, and a length direction, indicated as L, wherein, in the example shown, the width of the transistors 150A, 150B may be 100 nm and less, while a length of the electrodes of the gate electrode structures 151 may be 40 nm and less. Furthermore, the transistors 150A, 150B may be embedded into an interlayer dielectric material, which for convenience is not illustrated in FIG. 1a. Additionally, contact elements 161A, 161B are provided so as to connect to the active regions 102A, 102B, respectively, at the drain side and source side of the transistors 150A, 150B. In the example shown, a single contact element 161A may be provided to connect to the drain of the transistor 150A and a single contact element 161A to connect to the source of the transistor 150A due to the reduced width of the transistor 150A. Likewise, a single contact element 161B connects to the drain region and a single contact element 161B connects to the source region of the transistor 150B. Consequently, the presence of the contact elements 161A, 161B in close proximity to the drain and source regions may have an influence on the overall strain conditions in the channel region of the transistors 150A, 150B, in particular if a highly stressed dielectric material of the interlayer dielectric material may have to be provided with a reduced thickness and thus with a reduced amount due to deposition related restrictions, as explained above. Furthermore, the contact elements 161A, 161B may themselves be formed on the basis of, for instance, tungsten which may be deposited so as to exhibit a tensile internal stress component, which may thus also have influence on the overall strain conditions in the channel regions of the transistors 150A, 150B.
FIG. 1b schematically illustrates a cross-sectional view of the device of FIG. 1a according to the line Ib. As illustrated, the device 100 comprises a substrate 101, such as a silicon substrate or any other appropriate carrier material, above which is formed a silicon-based semiconductor layer 102. The semiconductor layer 102 comprises the active regions 102A, 102B and portions of the isolation structure 103 (not shown) so as to appropriately define the size and shape of the active regions 102A, 102B. Moreover, drain and source regions 152 are formed in the active regions 102A, 102B in accordance with the overall transistor characteristics. That is, highly N-doped drain and source regions are provided in the transistor 150A and highly P-doped drain and source regions 152 are provided in the transistor 150B. Furthermore, in order to reduce the contact resistivity and the overall series resistance in the transistors 150A, 150B, a metal silicide material 154, such as a nickel silicide, a nickel/platinum silicide and the like, is typically formed in the drain and source regions and acts as a contact area for connecting to the contact elements 161A, 161B, respectively. Furthermore, as shown, the gate electrode structures 151 may have any appropriate configuration and may comprise a gate electrode 151A that is separated from a channel region 153 by a gate dielectric material 151B. Furthermore, if required, a spacer structure 151C may be included in the gate electrode structures 151. Additionally, a contact level 160, which may be understood as the combination of any appropriate interlayer dielectric material and the corresponding contact elements 161A, 161B, is formed to encapsulate and thus passivate the transistors 150A, 150B while at the same time providing electrical contact via the contact elements 161A, 161B such that the contact level 160 acts as an “interface” between the circuit elements formed in and above the semiconductor layer 102, such as the transistors 150A, 150B, and a metallization system (not shown) formed or to be formed on the contact level 160 and comprising a network of metal lines and vias for establishing the required electrical connections. As discussed above, the contact level 160 comprises a strain-inducing material 162A formed above the transistor 150A in order to induce a desired strain component therein. Similarly, a strain-inducing material 162B is formed above the transistor 150B and provides a desired strain component. Additionally, a further dielectric material 163 is typically provided in accordance with the overall device requirements.
The semiconductor device 100 as shown in FIGS. 1a and 1b may be formed on the basis of the following processes. After forming the isolation structure 103, the basic configuration of the active regions 102A, 102B may be established by well-known implantation processes in combination with appropriate masking regimes. Thereafter, the gate electrode structures 151 are formed by providing one or more appropriate materials for the gate dielectric material 151B, which may include high-k dielectric materials, i.e., dielectric materials having a dielectric constant of 10.0 or higher, possibly in combination with “conventional” dielectric materials, such as silicon oxide based materials and the like. Similarly, the gate electrode material 151A may be formed, for instance, by using a placeholder material, if sophisticated metal-containing electrode materials are to be provided in a later manufacturing stage. In other cases, the electrode material 151A may comprise a work function adjusting species, in combination with polysilicon, silicon, silicon/germanium and the like, depending on the overall process strategy. It should further be appreciated that additional materials, such as dielectric cap materials, hard mask materials and the like, may also be deposited in combination with the electrode material 151A, depending on the overall process strategy. Thereafter, sophisticated lithography and etch techniques may be applied in order to obtain the gate electrode 151A with a desired critical dimension in accordance with the design rules. Thereafter, the drain and source regions 152 may be formed on the basis of ion implantation, epitaxial growth techniques, a combination thereof and the like, as is required for achieving the desired transistor characteristics. For example, frequently, a strain-inducing semiconductor alloy may be provided in one or both of the transistors 150A, 150B so as to obtain a desired high strain component in the channel region 153. For this purpose, an appropriate semiconductor alloy, such as silicon/germanium or silicon/carbon, may be incorporated into the active regions 102A or 102B, or both, possibly in an in situ doped state. Furthermore, the spacer structure 151C may be formed so as to provide a desired offset, for instance, with respect to introducing dopant species, forming the metal silicide regions 154 and the like. After completing the drain and source regions 152, the metal silicide regions 154 may be formed on the basis of well-established process techniques, wherein a portion of the gate electrode material 151A may also be converted into a metal silicide, if required, while in other cases the silicidation thereof may be suppressed by providing a corresponding cap material. Next, the layers 162A, 162B may be formed, possibly in combination with appropriate etch stop materials and the like, which for convenience are not shown. To this end, appropriate deposition techniques for forming silicon nitride material, nitrogencontaining silicon carbide material and the like may be applied in order to obtain the desired internal stress level of the layers 162A, 162B. As previously discussed, due to the reduced overall transistor dimensions and also due to the increasing packing density, the thickness of the layers 162A, 162B may be restricted by the overall device geometry so that, for a given maximum internal stress level achievable by presently available deposition techniques, the final strain level in the channel regions 153 may be less than desired. Thereafter, the material 163 may be deposited and planarized in order to prepare a substantially planar surface topography for the subsequent complex patterning process for forming the contact elements 161A, 161B. During the corresponding patterning process, an etch mask may be formed on the basis of sophisticated lithography techniques in order to define the lateral size and shape as well as position of the contact elements 161A, 161B, as is, for instance, shown in FIG. 1a. During the patterning process, the layer 163 may be etched first and subsequently an appropriate etch chemistry may be selected so as to etch through the layers 162A, 162B in order to finally expose a portion of the metal silicide regions 154. Thereafter, the corresponding openings may be filled with an appropriate contact metal, wherein frequently tungsten may be used in combination with an appropriate barrier material, such as titanium, titanium nitride and the like. The deposition of the tungsten material may typically be accomplished on the basis of a chemical vapor deposition (CVD) process, during which the material may deposit with a tensile stress component which may thus act on the transistors 150A, 150B and may therefore influence the final strain conditions in the channel regions 153. Thus, as previously explained, with the continuous shrinkage of the transistor dimensions, the effect of the layers 162A, 162B on the finally obtained strain conditions in the channel regions 153 may become increasingly less pronounced, while the contact elements 161A, 161B may increasingly influence the strain conditions and thus the overall performance of the transistors 150A, 150B. In this case, the tensile internal stress of the contact elements 161A may have a positive effect on the N-channel transistor 150A, while on the other hand, the P-channel transistor 150B may be negatively affected by the tensile stress of the contact elements 161B by, for instance, reducing any compressive strain component which may be induced by the layer 162B, or by any other compressive strain-inducing mechanism.
The present disclosure is directed to various devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.